Because memory cells have different cell currents, memory cells have different read speed values. Some memory cells are “regular” or have an average read speed value. Some memory cells are faster than an average memory cell or have a read speed value lower than the average read speed value. A fast (faster) memory cell is commonly called a strong memory cell. In contrast, some memory cells are slower than the average memory cell or have a read speed value higher than the average read speed value. A slow (slower) memory cell is commonly called a weak memory cell. When a memory cell is accessed, a strong memory cell sinks and/or sources a higher current, while a weak memory cell sinks and/or sources a lower current. As a result, the read speed of a memory cell can be identified by the current sunk and/or sourced by the memory cell.
Tracking circuits in a memory macro are used to generate tracking or reference signals based on which signals for reading memory cells are generated. Ideally, the signals generated by the tracking circuits cover the condition of the weakest (or “weak”) memory cells to be read. Generally, weak memory cells need relaxed access timing.
In an approach, the access timing for weak memory cells is simulated based on time delays of (logic) transistors manufactured by a logic manufacturing process, which is designed to manufacture transistors used in logic and/or control circuits. In contrast, a memory manufacturing process is designed to manufacture (memory) transistors used in memory devices. Generally, speed variations of logic transistors and of memory transistors do not correlate well. For example, in a memory macro, logic transistors may be fast while memory transistors may be slow or vice versa. As a result, in some conditions, accessing the weak memory cell with the time delays of logic transistors may not provide the desired timing.
Like reference symbols in the various drawings indicate like elements.